1. Field of the Invention
The present invention relates generally to a metal-metal capacitor (MMC), and particularly to a two side MMC (2-side MMC) having high capacitance density and method of making the same.
2. Description of the Prior Art
Various capacitive structures are used as electronic elements in integrated circuits such as radio frequency integrated circuits (RFIC), and monolithic microwave integrated circuits (MMIC). Such capacitive structures include, for example, metal-oxide-semiconductor (MOS) capacitors, p-n junction capacitors and metal-metal capacitor. The metal-metal capacitor has a metal-insulator-metal (MIM) structure exhibiting improved frequency and temperature characteristics. Furthermore, it can be formed in the metal interconnect layers, thereby to be integrated with the CMOS transistor FOL process. A metal-metal capacitor typically includes a capacitor dielectric layer disposed between lower and upper electrodes and usually needs a rather large area in a die. To increase the circuit density and reduce the cost, large capacitance density is highly desirable. One known method for increasing the capacitance density is to reduce the dielectric thickness. However, the effect is limited since reducing the dielectric thickness generates problems such as undesired high leakage current and poor RF loss tangent. Another approach is to use high dielectric constant dielectrics.
In order to increase the capacitance density, a metal-insulator-metal (MIM) capacitor and a method of making the same are disclosed in U.S. Pat. No. 6,977,198 assigned to the same assignee of the present invention and incorporated herein entirely for reference. As shown in FIG. 1, an MIM capacitor 10 comprises a metal layer 12 disposed on a substrate 100, a metal layer 14 disposed above the metal layer 12 and electrically isolated from the metal layer 12 with a capacitor dielectric layer 13, wherein like reference numerals refer to similar or corresponding elements, regions, and portions. A metal layer 16 is disposed above the metal layer 14 and is electrically isolated from the metal layer 14 with a capacitor dielectric layer 15. A cap layer 22 is deposited on the metal layer 16. The cap layer 22 may be made of silicon oxide or silicon nitride. The MIM capacitor 10 is covered with an IMD layer 120. The metal layer 12, the capacitor dielectric layer 13, and the metal layer 14 constitute a first capacitor (C1). The metal layer 14, the capacitor dielectric layer 15, and the metal layer 16 constitute a second capacitor (C2). The metal layer 12 of the MIM capacitor 10 is electrically connected to a conductive terminal 42 through a metal via 31 that penetrates through the IMD layer 120. The metal layer 14 is electrically connected to a conductive terminal 44 through at least one metal via 32. The metal layer 16 is electrically connected to the conductive terminal 42 through at least one metal via 33 that penetrates through the IMD layer 120 and the cap layer 22.
In a method of making the aforesaid MIM capacitor structure, as shown in FIG. 2, a lithographic process and an anisotropic dry etching process are carried out to etch a stack of the capacitor dielectric layer 13, the metal layer 14, the capacitor dielectric layer 15, the metal layer 16, and the cap layer 22, to form the upper capacitor structure 50 and a part of the lower capacitor structure. The etching stops on the metal layer 12 after the capacitor dielectric layer 13 is etched through. Thereafter, as shown in FIG. 3, a photo resist layer is coated on the metal layer 12 and covers the upper capacitor structure 50 and then patterned to form a photo mask 60a. A metal etching process is performed to etch away the portion of the metal layer 12 not covered by the photo mask 60a, to form a lower capacitor structure 70 and metal interconnect conductive wire. A portion of the cap layer 22 and the underlying metal layer 16 of the upper capacitor structure 50 that are not covered with the photo mask 60a are also etched away in this etching process. Using the cap layer 22 and the metal layer 16 as an etching buffer, the etching can be stopped at the capacitor dielectric layer 15 to complete the configuration of the upper capacitor structure 50. The metal layer 14 has an area smaller than that of the metal layer 12. The metal layer 16 has an area smaller than that of the metal layer 14.
However, the stop of the etching at the capacitor dielectric layer 15 becomes a critical process step due to the narrow process window. The ideal condition is to stop the etching at the capacitor dielectric layer 15 and remain an about 100 angstrom-thick capacitor dielectric layer 15. However, the utilization of the cap layer 22 and the metal layer 16 as an etching buffer leads to a narrow process window, due to different etching performances for different reaction chambers, and variant film properties, thicknesses, or etching rates of the cap layer 22 and the metal layer. These variations cause the etching results to be unstable and hard controlled. FIG. 4 illustrates an example of an insufficient etching stopping at the metal layer 16. FIG. 5 illustrates an example of an over etching stopping at the metal layer 14.
Therefore, a novel metal-metal capacitor as well as a method of making the same is still needed, to avoid the aforesaid disadvantages and attain an improved capacitance density.